1. Field
The present disclosure generally relates to the design of circuits typically employed by timing elements in modern computer systems. More specifically, the present disclosure relates to the design of a continuous phase-modification circuit based on an injection-locking mechanism to reduce phase variation in ring oscillators.
2. Related Art
As the distance between computing/memory nodes continues to increase, long-distance off-chip and on-chip communication is becoming a more-prevalent concern for system designers. At the same time, in order to improve system performance, data rates are increasing. A common technology underlying this long-distance/fast data-rate communication facilitates the retiming of data via amplifying latches to restore signal integrity (e.g., such as in a transmitter and receiver setting, where the phases of the transmitting and receiving ends are arbitrary).
Retiming of synchronous data usually involves some form of phase adjustment of a local clock to synchronize it with the incoming data stream. During this process, the local clock is adjusted to sample at the middle (or within a time window) of the data eye (e.g., the edge from a DLL must be within 5 ps of the ideal sampling point). Clock phase alignment is usually accomplished by using a phase-locked loop (PLL) or a delay-locked loop (DLL). Because faster data rates imply an ever-shrinking data eye, there is a corresponding tighter demand on the position of the sampling edges generated from PLLs and DLLs. Moreover, because noise inherent in systems tends to widen the phase window of PLLs and DLLs, this means that the distribution of edges around the ideal sampling point becomes wider, which makes it harder to meet the constraints of an edge falling in a certain time window. Therefore, lowering the output clock jitter from PLLs and DLLs is of paramount importance.
FIG. 1 presents a block diagram illustrating an existing PLL, which generates a clock signal via an oscillator. This PLL adjusts the phase and frequency so that, when locked, both the frequency and the phase of the multiplied clock from the voltage-controlled oscillator (VCO) are in sync with the reference input to the PLL. In particular, the feedback control is split into a frequency-control path and a phase-control path. The frequency-control path detects a frequency error and integrates this error to drive it to zero. Alternatively, the phase-control path provides a linear proportional correction to the phase. The feedback-control loop compares a divided clock in an oscillator to a reference clock. When the edges of the divided clock and reference clock do not match, the control loop speeds up or advances the phase and slows down or retards the phase accordingly to allow the oscillator edge to synchronize with the reference edge. Typically the reference frequency is many times smaller than the oscillator frequency. Moreover, in order to maintain feedback-loop stability, the frequency of the control loop is many times smaller than the reference frequency. This implies that it takes a long time for the accumulated phase error to be corrected, a time on the order of several loop time constants. By adjusting the phase correction strength, the amount of phase adjustment in one reference clock cycle can be increased at the cost of incurring a larger dither during stable operation.
Hence, what is needed is a phase-modification circuit without the above-described problems.